In recent years, as a method by which semiconductor elements having connecting terminals in a large number are connected and packaged in a high density on a wiring-circuit board (motherboard), a BGA (ball grid array) package of an OMPAC (overmolded packaging) system has been developed and is being put into practical use, according to which chips are mounted on an organic wiring board, pads on the chips are connected to connecting terminals on the side of the organic wiring board by gold-wire wire bonding, thereafter the whole semiconductor chips are covered with an organic insulating sealing material, and solder balls are arranged in arrays on the back of the organic wiring board to provide external terminals.
This structure can make the number of external terminals larger per unit area than conventional QFPs having a structure wherein chips are mounted on a metal lead frame and gold-wire wire bonding is carried out, thereafter the whole is sealed, and the external terminals are cut and formed so as to extend out of the sides of sealed portions. This has a characteristic feature that surface-mounted packaging on the motherboard by solder reflowing can be carried out with ease. However, since this requires gold-wire bonding, the size of semiconductor pads to be connected must be limited to about 80 .mu.m and also a certain distance must be ensured between the pad and the wiring terminal. Accordingly, its external size can not help being as large as 40 mm square or more in order to form a BGA package having i/o terminals of 500 pins or more. This structure has had a limit for situations a needing much more pins and on packaging on the motherboard in a higher density.
Meanwhile, in order to meet the need for higher-density packaging of semiconductor chips each having 500 pins or more, a flip-chip bonding system is proposed (C4) in which metal plating for various barriers is applied to bonding pads of a semiconductor chip and thereafter solder bumps are formed, followed by heat-melt face-down bonding to the terminals on the side of the wiring board through the bumps. Application of this system is partly put forward in ceramic substrates. However, it is forecasted that the process up to the formation of solder bumps on the pads of the semiconductor chip has so many steps as to result in a very high cost of semiconductor chips, that the stress due to temperature cycling is concentrated on solder bumps unless the gap between the chip surface and the wiring board is filled with resin, that the processing and management of such filling with resin are troublesome, and that an attempt to use it to connect bumps to the organic wiring board may result in greater difference in coefficient of linear expansion between bumps and chips to make the stress greater. Accordingly, the flip-chip bonding of i/o terminals of 500 pins or more is not actually available at present.
Meanwhile, a method is proposed in which gold wires are wire-bonded to the bonding pads of a semiconductor chip and are cut at positions close to necks so that gold bumps can be formed on chips at a lower cost (i.e., stud bumps). However, in order to connect and package such chips on the wiring board by face-down bonding, it is essential to use a process in which an organic conductive adhesive is coated on the stud bumps and, after connection and curing, the gap between the chip surface and the wiring board is filled with resin. Also, there remains a problem that the process has a large number of steps since it requires the step of gold-wire bonding for each chip, and also that the size of the pads of chips is limited to 80 .mu.m square and can not be made larger than that.